A digital data processing system may comprise several basic units: a central processing unit, a main memory, one or more input/output devices, and an input/output controller. The central processing unit (CPU) performs arithmetic and logic functions, the main memory stores program instructions and data, the I/O units interface peripheral devices and remote users to the system, and the I/O controller coordinates the activities of the I/O units.
There is an ever increasing need for larger capacity, larger throughput systems to meet the growing needs of data processing users. Processing speeds as well as data capacity have increased. One limitation of system size has been the cost of high speed main memories. Such memories are still considerably faster than larger capacity but slower bulk memories such as magnetic disks and tapes.
Since a user needs only a portion of his program and data in storage for execution at any given time, the concept of program segmentation and memory paging evolved. With these techniques, the "virtual memory" available to the processing of tasks by the system appears greater than the real main memory.
By calling only a portion of the user's program and data into execution at any given time, the capacity requirements of the main memory are reduced. Further, the use of pages for memory storage permits greater flexibility in memory use, since a page may be stored wherever space permits, without the need for storing all related pages together. Such overhead functions as periodic memory compacting, for example, are eliminated. User security is also enhanced through the use of memory paging.
A computer memory management unit (MMU) is the name given to the portion of the above-described system which is responsible for permitting the physical main memory to be shared by multiple system and user programs or tasks.
A MMU maps the logical address, i.e. the memory address as seen by any given program or task, into the actual physical address space of the CPU. This makes the address space of each task independent of physical memory locations. The MMU also provides protection of each task's memory space from access by another task unless such sharing is explicitly allowed.
MMU's are known which are primarily concerned with minimizing the fragmentation of memory that results from the switching in and out of tasks. Other MMU's are known which provide tasks with logical memory spaces larger than the actual size of the processor's physical memory. MMU's have supported paging and segmentation memory management techniques to accomplish these purposes. Processor using such techniques often employ page tables in the system main memory, which tables comprise pointers which translate the address of each block of each task's logical address space into a physical address. Hardware registers are used to hold a subset of these page tables in order to minimize the amount of time-consuming accesses to pointers in the main memory. This mechanism relies on each task controlling the CPU for a lengthy time period and relies on high hit rates within any given task--i.e. it assumes that most memory references by a given task will be in the same general area of memory, thus minimizing swapping in and out of memory pages. In actuality, in such systems the CPU performance is degraded.
The present invention represents an improvement over known memory management units, in that it provides for very rapid switching between tasks, in addition to minimizing fragmentation and performing the other duties of a memory management unit. The present invention is used in a paged memory system in which a large number of coresident tasks each has a pointer which is stored in a hardware register. These registers are addressed directly by an identifying number assigned to the active task.
Task switching is accomplished rapidly by merely changing the contents of a register which holds the task number of the active task.
A separate register holds the task number of the executive task, so that the system can automatically switch back and forth between the executive task and the active user task.
The register set is of such size as to allow multiple tasks to have their full sets of descriptors held in fast register files. This enables high performance execution, fast task switches, and fast access by the executive data in program address space. It also enables I/O to be mapped through a range of program address spaces with the same speed as the CPU.
In a preferred embodiment of the present invention, tasks are of a predetermined maximum size. The MMU contains a software addressable register which establishes the size and number of coresident tasks which can be addressed through the MMU. This permits the system to be configured for use in environments demanding differing sizes and numbers of coresident tasks. The executive task can be up to 4 times larger than a user task.
In known MMU's employing standard paging techniques, as opposed to demand paging techniques, each task must be loaded in its entirety into main memory. The size of a task cannot change after memory loading has occurred.
The present invention provides an improved MMU which improves upon prior page oriented MMU's in that it provides for generation of an interrupt on access to a specified page. In this way, the CPU is notified that a task's memory requirements are expanding and that the memory previously assigned to the task is approaching the maximum boundary. Thus the operating system can either terminate the task or assign in more memory.
The MMU of the present invention also allows direct memory accesses into the address space of any task, thus making the system very efficient in applications requiring extensive I/O.